Method of fabricating semiconductor structure using planarization process and cleaning process
US9748111B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Feb 1, 2016 |
| Grant date | Aug 29, 2017 |
| Priority date | — |
| Expiry date | Feb 1, 2036 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D86/011
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method for fabricating a semiconductor structure includes following steps. First, a first layer, a second layer and a third layer are sequentially formed on the substrate. The second layer is conformally disposed on the top surface of the first layer. The second layer and the first layer have different compositions, and the third layer and the second layer also have different compositions. Then, a planarizing process is performed on the third layer until portions of the second layer are exposed. Afterwards, hydrofluoric acid and aqueous oxidant are concurrently or sequentially provided to the remaining second and third layers. Finally, an etch back process is carried out to remove all the second layer and portions of the first layer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.