Shadow pad for post-passivation interconnect structures

US9748212B2 · kind B2 · utility

Assignee

• TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD. · TW

Inventors

• Shih-Wei Liang · Yuanli, TW
• Bor-Rung Su · New Taipei, TW
• Chang-Pin Huang · Daxi District, TW
• Chien-Chia Chiu · Pingzhen District, TW
• Hsien-Ming Tu · Zhubei City, TW
• Chun-Hung Lin · New Taipei, TW
• Yu-Chia Lai · Zhunan Town, TW

Key dates

• Filing date: Apr 30, 2015
• Grant date: Aug 29, 2017
• Expiry date: Apr 30, 2035

Classification

• Technology area (CPC H): Electricity
• CPC primary: H01L2225/1058
• WIPO field: Semiconductors
• WIPO sector: Electrical engineering

Abstract

Interconnect structures, packaged semiconductor devices, and methods of packaging semiconductor devices are disclosed. In some embodiments, an interconnect structure includes a first post-passivation interconnect (PPI) layer. The first PPI layer includes a landing pad and a shadow pad material proximate the landing pad. A polymer layer is over the first PPI layer, and a second PPI layer is over the polymer layer. The second PPI layer includes a PPI pad. The PPI pad is coupled to the landing pad by a via in the polymer layer. The shadow pad material is proximate the PPI pad and comprises a greater dimension than a dimension of the PPI pad. The shadow pad material is disposed laterally around the PPI pad.