Gate with self-aligned ledged for enhancement mode GaN transistors
US9748347B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jul 30, 2014 |
| Grant date | Aug 29, 2017 |
| Priority date | — |
| Expiry date | Oct 2, 2034 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D62/8503
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
An enhancement-mode GaN transistor with reduced gate leakage current between a gate contact and a 2DEG region and a method for manufacturing the same. The enhancement-mode GaN transistor including a GaN layer, a barrier layer disposed on the GaN layer with a 2DEG region formed at an interface between the GaN layer and the barrier layer, and source contact and drain contacts disposed on the barrier layer. The GaN transistor further includes a p-type gate material formed above the barrier layer and between the source and drain contacts and a gate metal disposed on the p-type gate material, with wherein the p-type gate material including comprises a pair of self- aligned ledges that extend toward the source contact and drain contact, respectively.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.