Vertical transistor including a bottom source/drain region, a gate structure, and an air gap formed between the bottom source/drain region and the gate structure
US9748380B1 · kind B1 · utility
25Cited by
11References
11Claims
0Family size
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Key dates
| Filing date | Jun 29, 2016 |
| Grant date | Aug 29, 2017 |
| Priority date | — |
| Expiry date | Jun 29, 2036 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2201/84
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A vertical transistor includes a fin structure formed on a substrate, a gate structure formed on the fin structure, and a bottom source/drain (S/D) region formed on the fin structure, such that an air gap is formed between the bottom S/D region and the gate structure.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.