Method for semiconductor device fabrication with improved source drain epitaxy
US9748389B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 21, 2016 |
| Grant date | Aug 29, 2017 |
| Priority date | — |
| Expiry date | Jun 21, 2036 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D86/011
Abstract
A method includes receiving a precursor having a substrate and first and second pluralities of gate structures, the first pluralities having a greater pitch than the second pluralities. The method further includes depositing a dielectric layer covering the substrate and the first and second pluralities; and performing an etching process to the dielectric layer. The etching process removes a first portion of the dielectric layer over the substrate, while a second portion of the dielectric layer remains over sidewalls of the first and second pluralities. The second portion of the dielectric layer is thicker over the sidewalls of the second plurality than over the sidewalls of the first plurality. The method further includes etching the substrate to form third and fourth pluralities of recesses adjacent the first and second pluralities, respectively; and epitaxially growing fifth and sixth pluralities of semiconductor features in the third and fourth pluralities, respectively.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.