Integrated circuit (IC) design analysis and feature extraction
US9754071B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Feb 19, 2016 |
| Grant date | Sep 5, 2017 |
| Priority date | — |
| Expiry date | Feb 19, 2036 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F30/398
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Various embodiments include approaches for analyzing integrated circuit (IC) designs. In some cases, an approach includes: defining extraction parameters for the design of the IC for each of a set of failure modes; testing the design of the IC for a failure mode in the set of failure modes; identifying a defined extraction parameter from the design of the IC for at least one of the set of failure modes; correlating the identified defined extracted parameter and each of the at least one failure mode for the design of the IC; and creating a normalized parameter equation representing the correlation of the identified defined extraction parameter with the at least one failure mode for the design of the IC in numerical form.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.