Memory device and method for fabricating the same
US9754790B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | May 14, 2015 |
| Grant date | Sep 5, 2017 |
| Priority date | — |
| Expiry date | May 14, 2035 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D62/83
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A memory device comprises a patterned multi-layers stacking structure, a semiconductor capping layer, a memory layer and a channel layer. The patterned multi-layers stacking structure is formed on a substrate and has at least one trench used to define a plurality of ridge-shaped stacks comprising at least one conductive strip in the patterned multi-layers stacking structure. The semiconductor capping layer covers on the ridge-shaped stacks. The memory layer covers on sidewalls of the trench. The channel layer covers on the memory layer, the semiconductor capping layer and a bottom of the trench, wherein the channel layer is directly in contact with the semiconductor capping layer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.