Semiconductor chip including a chip level based on a layout that includes both regular and irregular wires
US9754878B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | May 20, 2013 |
| Grant date | Sep 5, 2017 |
| Priority date | — |
| Expiry date | Feb 20, 2034 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY02P90/02
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A plurality of regular wires are formed within a given chip level, each having a linear-shape with a length extending in a first direction and a width extending in a second direction perpendicular to the first direction. The plurality of regular wires are positioned according to a fixed pitch such that a distance as measured in the second direction between lengthwise centerlines of any two regular wires is an integer multiple of the fixed pitch. At least one irregular wire is formed within the given chip level and within a region bounded by the plurality of regular wires. Each irregular wire has a linear-shape with a length extending in the first direction and a width extending in the second direction. A distance as measured in the second direction between lengthwise centerlines of any irregular wire and any regular wire is not equal to an integer multiple of the fixed pitch.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.