Stacked semiconductor package and manufacturing method thereof
US9754892B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 28, 2012 |
| Grant date | Sep 5, 2017 |
| Priority date | — |
| Expiry date | Jan 31, 2033 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/18162
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Disclosed herein is a stacked semiconductor package in which semiconductor chips having various sizes are stacked. In accordance with one aspect of the present disclosure, a stacked semiconductor package includes a first semiconductor chip structure provided with a first semiconductor chip, a first mold layer surrounding the first semiconductor chip, and a first penetration electrode passing through the first mold layer and electrically connected to the first semiconductor chip, and a second semiconductor chip structure vertically stacked on the first semiconductor chip structure and provided with a second semiconductor chip and a second penetration electrode electrically connected to the first penetration electrode, wherein the first semiconductor chip structure may have the same size as the second semiconductor chip structure.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.