Methods of forming semiconductor devices including determining misregistration between semiconductor levels and related apparatuses
US9754895B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 7, 2016 |
| Grant date | Sep 5, 2017 |
| Priority date | — |
| Expiry date | Mar 7, 2036 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2225/06548
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method of determining a lateral misregistration between levels of a semiconductor structure comprises imaging at least one first alignment mark in a first level of the structure and at least one second alignment mark in a second level of the structure. A digital image of the first and second alignment marks is formed, each of which are defined by a set of points having an x-value and a y-value. The x-values and y-values of points defining the first alignment mark and points defining the second alignment mark are averaged to determine a center of the first alignment mark and a center of the second alignment mark. An x-coordinate and a y-coordinate of the center of the first alignment mark is subtracted from the respective x-coordinate and y-coordinate of the center of the second alignment mark to determine a lateral misregistration between the first level and the second level. Related methods of forming a semiconductor wafer, semiconductor assembles and metrology tools for use in implementing the methods are disclosed.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.