Final passivation for wafer level warpage and ULK stress reduction
US9754905B1 · kind B1 · utility
4Cited by
5References
6Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Oct 13, 2016 |
| Grant date | Sep 5, 2017 |
| Priority date | — |
| Expiry date | Oct 13, 2036 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/35121
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Embodiments are directed to a method of forming a semiconductor chip package and resulting structures having an annular PSPI region formed under a BLM pad. An annular region is formed under a barrier layer metallurgy (BLM) pad. The annular region includes a photosensitive polyimide (PSPI). A conductive pedestal is formed on a surface of the BLM pad and a solder bump is formed on a surface of the conductive pedestal. The annular PSPI region reduces wafer warpage and ULK peeling stress.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.