Method of forming wafer-level molded structure for package assembly
US9754917B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jul 13, 2015 |
| Grant date | Sep 5, 2017 |
| Priority date | — |
| Expiry date | Jul 13, 2035 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/19041
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method of forming an integrated circuit structure is provided. In an embodiment, the method includes bonding top dies onto a bottom wafer and then molding a first molding material onto and in between the top dies and the bottom wafer. The bottom wafer, the top dies, and the first molding material are sawed to form molding units. Each of the molding units includes one of the top dies and a bottom die sawed from the bottom wafer. The molding units are bonded onto a package substrate and a second molding material is molding onto the one of the molding units and the package substrate. Thereafter, the package substrate and the second molding material are sawed to form package-molded units.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.