Semiconductor device with substantially equal impurity concentration JTE regions in a vicinity of a junction depth
US9755014B2 · kind B2 · utility
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Key dates
| Filing date | Sep 28, 2016 |
| Grant date | Sep 5, 2017 |
| Priority date | — |
| Expiry date | Sep 28, 2036 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D64/64
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A highly reliable semiconductor device with high withstand voltage is provided. As means therefor, an impurity concentration in a first JTE region is set to 4.4×1017 cm−3 or higher and 6×1017 cm−3 or lower and an impurity concentration in a second JTE region is set to 2×1017 cm−3 or lower in a case of a Schottky diode, and an impurity concentration in the first JTE region is set to 6×1017 cm−3 or higher and 8×1017 cm−3 or lower and an impurity concentration in the second JTE region is set to 2×1017 cm−3 or lower in a case of a junction barrier Schottky diode.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.