Merged gate for vertical transistors
US9755071B1 · kind B1 · utility
7Cited by
7References
15Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jun 30, 2016 |
| Grant date | Sep 5, 2017 |
| Priority date | — |
| Expiry date | Jun 30, 2036 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D84/83
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Embodiments of the present invention are directed to a method of forming a conductive via. The method includes forming an opening in a substrate and forming a conductive material along sidewall regions of the opening, wherein the conductive material occupies a first portion of an area within the opening. The method further includes forming an insulating fill in a second portion of the area within the opening, wherein at least one surface of the conductive material and at least one surface of the insulating fill are substantially coplanar with a front surface of the substrate.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.