Methods of making memory devices with programmable impedance elements and vertically formed access devices
US9755142B1 · kind B1 · utility
Assignee
Inventor
Key dates
| Filing date | May 16, 2016 |
| Grant date | Sep 5, 2017 |
| Priority date | — |
| Expiry date | May 16, 2036 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C14/009
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method can include forming a plurality of access transistors, including forming second semiconductor regions over an integrated circuit substrate that are doped to a second conductivity type, the second semiconductor regions being over and in contact with first semiconductor regions doped to a first conductivity type, and forming third semiconductor regions doped to the first conductivity type in contact with the second semiconductor regions; forming a plurality of conductive structures, over and in contact with the third semiconductor regions; and forming programmable impedance memory cells over and in contact with the conductive structures.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.