Sense amplifier and latching scheme
US9761285B1 · kind B1 · utility
2Cited by
15References
19Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Feb 26, 2016 |
| Grant date | Sep 12, 2017 |
| Priority date | — |
| Expiry date | Feb 26, 2036 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C11/419
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Approaches for a circuit are provided. The circuit includes a sense amplifier circuit which includes a plurality of transistors enabled by a sense amplifier enable signal to output a first output data line true signal and a second output data line complement signal to a latching circuit, and the latching circuit which includes a primary driver actively driven by the first output data line true signal and a secondary driver actively driven by the second output data line complement signal such that the latching circuit outputs a read global data line.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.