Patent · US Active

Method of manufacturing an integrated circuit having field effect transistors including a peak in a body dopant concentration

US9761665B2 · kind B2 · utility

0Cited by

6References

18Claims

0Family size

Assignee

Infineon Technologies AG · DE

Inventors

Thorsten Meyer · Regensburg, DE
Stefan Decker · Munich, DE
Norbert Krischke · Munich, DE
Christoph Kadow · Gauting, DE

Key dates

Filing date	May 18, 2016
Grant date	Sep 12, 2017
Priority date	—
Expiry date	May 18, 2036

Classification

Technology area (CPC H)Electricity
CPC primaryH10D84/83
WIPO fieldSemiconductors
WIPO sectorElectrical engineering

Abstract

An integrated circuit having field effect transistors and manufacturing method. One embodiment provides an integrated circuit including a first FET and a second FET. At least one of source, drain, gate of the first FET is electrically connected to the corresponding one of source, drain, gate of the second FET. At least one further of source, drain, gate of the first FET and the corresponding one further of source, drain, gate of the second FET are connected to a circuit element, respectively. A dopant concentration of a body along a channel of each of the first and second FETs has a peak at a peak location within the channel.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.