Reconfigurable phase-locked loop
US9762249B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Jul 29, 2016 |
| Grant date | Sep 12, 2017 |
| Priority date | — |
| Expiry date | Jul 29, 2036 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03L2207/50
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A reconfigurable, digital phase-locked loop integrated circuit is disclosed which is coupleable to a reference frequency generator. A representative embodiment may include a memory storing a plurality of configuration parameters, at least one configuration parameter of specifying an output frequency; a reconfigurable frequency and delay generator configurable and reconfigurable in response to the configuration parameters to generate an output signal having the output frequency; and a digital controller adapted to access the memory and retrieve the plurality of configuration parameters, and to generate a plurality of control signals to the reconfigurable frequency and delay generator both to generate the output signal having the output frequency in response to the plurality of configuration parameters, and to match a phase of the output signal to an input signal phase.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.