Opportunity multithreading in a multithreaded processor with instruction chaining capability
US9766895B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Nov 12, 2014 |
| Grant date | Sep 19, 2017 |
| Priority date | — |
| Expiry date | Jun 19, 2035 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F9/46
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A computing device determines that a current software thread of a plurality of software threads having an issuing sequence does not have a first instruction waiting to be issued to a hardware thread during a clock cycle. The computing device identifies one or more alternative software threads in the issuing sequence having instructions waiting to be issued. The computing device selects, during the clock cycle by the computing device, a second instruction from a second software thread among the one or more alternative software threads in view of determining that the second instruction has no dependencies with any other instructions among the instructions waiting to be issued. Dependencies are identified by the computing device in view of the values of a chaining bit extracted from each of the instructions waiting to be issued. The computing device issues the second instruction to the hardware thread.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.