Semiconductor memory device and memory system
US9767910B1 · kind B1 · utility
20Cited by
6References
20Claims
0Family size
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Key dates
| Filing date | Sep 13, 2016 |
| Grant date | Sep 19, 2017 |
| Priority date | — |
| Expiry date | Sep 13, 2036 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2211/5648
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A semiconductor memory device includes: a first memory unit including first to fourth memory cells; a second memory unit including fifth to eighth memory cells; a first word line coupled to gates of the first and fifth memory cells; a second word line coupled to gates of the second and sixth memory cells; a third word line coupled to gates of the third and seventh memory cells; and a fourth word line coupled to gates of the fourth and eighth memory cells. In a write operation, writes to the fourth memory cell, the first memory cell, the eighth memory cell, and the fifth memory cell are executed in order.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.