Systems and methods for testing a semiconductor memory device having a reference memory array
US9767919B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Apr 15, 2016 |
| Grant date | Sep 19, 2017 |
| Priority date | — |
| Expiry date | Apr 15, 2036 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2029/1802
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Semiconductor memory testing devices and methods are disclosed. In one respect, a device is disclosed that includes a first memory cell array having a first bit-line and a plurality of first memory cells connected to the first bit-line; a second memory cell array having a second bit-line and a plurality of second memory cells connected to the second bit-line, the number of second memory cells being smaller than that of the first memory cells; a sense amplifier connected to the first bit-line and a first end of the second bit-line; a word decoder configured to operate the second memory cells responsive to a first test signal; and a transistor coupled to a second end of the second bit-line and operated by a second test signal.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.