Semiconductor device having dual channels, complementary semiconductor device and manufacturing method thereof
US9768073B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Feb 26, 2016 |
| Grant date | Sep 19, 2017 |
| Priority date | — |
| Expiry date | Feb 26, 2036 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D84/853
Abstract
Provided is a semiconductor device having dual channels including a first portion and a second portion sharing a buried gate pillar. The buried gate pillar extends from a first surface of a substrate toward a second surface opposite to the first surface. The first portion includes the buried gate pillar, a first gate dielectric layer at a first sidewall of the buried gate pillar and a first doped region set aside the first gate dielectric layer. A first channel is provided in the substrate between the first gate dielectric layer and the first doped region set. The second portion includes the buried gate pillar, a second gate dielectric layer at a second sidewall of the buried gate pillar and a second doped region set aside the second gate dielectric layer. A second channel is provided in the substrate between the second gate dielectric layer and the second doped region set.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.