Thermal pads between stacked semiconductor dies and associated systems and methods
US9768147B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Feb 3, 2014 |
| Grant date | Sep 19, 2017 |
| Priority date | — |
| Expiry date | Feb 3, 2034 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/10253
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Systems and methods are described for improved heat dissipation of the stacked semiconductor dies by including metallic thermal pads between the dies in the stack. In one embodiment, the thermal pads may be in direct contact with the semiconductor dies. Heat dissipation of the semiconductor die stack can be improved by a relatively high thermal conductivity of the thermal pads that directly contact the adjacent silicon dies in the stack without the intervening layers of the low thermal conductivity materials (e.g., passivation materials). In some embodiments, the manufacturing yield of the stack can be improved by having generally coplanar top surfaces of the thermal pads and under-bump metallization (UBM) structures.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.