Semiconductor structure with integrated passive structures
US9768195B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 29, 2016 |
| Grant date | Sep 19, 2017 |
| Priority date | — |
| Expiry date | Jun 29, 2036 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D84/00
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A metal-oxide-semiconductor field-effect transistor (MOSFET) with integrated passive structures and methods of manufacturing the same is disclosed. The method includes forming a stacked structure in an active region and at least one shallow trench isolation (STI) structure adjacent to the stacked structure. The method further includes forming a semiconductor layer directly in contact with the at least one STI structure and the stacked structure. The method further includes patterning the semiconductor layer and the stacked structure to form an active device in the active region and a passive structure of the semiconductor layer directly on the at least one STI structure.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.