Pad structure layout for semiconductor device
US9768221B2 · kind B2 · utility
6Cited by
11References
19Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jun 27, 2013 |
| Grant date | Sep 19, 2017 |
| Priority date | — |
| Expiry date | Jun 27, 2033 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/13091
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A semiconductor device including a light sensing region disposed on a substrate is provided that includes a bond structure having one or more patterned layers underlying the pad element. The pad element may be coupled to the light sensing region and may be formed in a first metal layer disposed on the substrate. A second metal layer of the device has a first bond region, a region of the second metal layer that underlies the pad element. This first bond region of the second metal layer includes a pattern of a plurality of conductive lines interposed by dielectric. A via connects the pad element and the second metal layer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.