Semiconductor memory device
US9768265B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 15, 2016 |
| Grant date | Sep 19, 2017 |
| Priority date | — |
| Expiry date | Sep 15, 2036 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D64/693
Abstract
According to one embodiment, a semiconductor memory device includes a semiconductor layer, a first electrode, first and second oxide layers, and a storage layer. The first oxide layer is provided between the semiconductor layer and the first electrode. The second oxide layer is provided between the first oxide layer and the first electrode. The storage layer is provided between the first and second oxide layers. The storage layer includes a first region including silicon nitride, a second region provided between the first region and the second oxide layer and including silicon nitride, and a third region provided between the first and second regions. The third region includes a plurality of first metal atoms. A first density of bond of the first metal atoms in the third region is lower than a second density of bond of the first metal atom and a nitrogen atom in the third region.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.