Fermi-level unpinning structures for semiconductive devices, processes of forming same, and systems containing same
US9768269B2 · kind B2 · utility
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31Claims
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Key dates
| Filing date | Sep 18, 2014 |
| Grant date | Sep 19, 2017 |
| Priority date | — |
| Expiry date | Jan 10, 2035 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10N70/883
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
An interlayer is used to reduce Fermi-level pinning phenomena in a semiconductive device with a semiconductive substrate. The interlayer may be a rare-earth oxide. The interlayer may be an ionic semiconductor. A metallic barrier film may be disposed between the interlayer and a metallic coupling. The interlayer may be a thermal-process combination of the metallic barrier film and the semiconductive substrate. A process of forming the interlayer may include grading the interlayer. A computing system includes the interlayer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.