Nancy Zelick
21Patents
8h-index
34Co-inventors
71Inventor score
Filing activity: Aug 10, 2004 → Sep 29, 2017
Most-cited inventions
| Patent | Title | Area | Cited by | Status |
|---|---|---|---|---|
| US7348284B2 | Non-planar pMOS structure with a strained channel region and an integrated strained CMOS flow | Emerging Cross-Sectional Technologies | 98 | Expired |
| US8211772B2 | Two-dimensional condensation for uniaxially strained semiconductor fins | Electricity | 60 | Active |
| US7960794B2 | Non-planar pMOS structure with a strained channel region and an integrated strained CMOS flow | Emerging Cross-Sectional Technologies | 15 | Active |
| US8558279B2 | Non-planar device having uniaxially strained semiconductor body and method of making same | Electricity | 11 | Active |
| US8872225B2 | Defect transferred and lattice mismatched epitaxial film | Electricity | 10 | Active |
| US9391181B2 | Lattice mismatched hetero-epitaxial film | Electricity | 9 | Active |
| US9029835B2 | Epitaxial film on nanoscale structure | Electricity | 9 | Active |
| US8334184B2 | Polish to remove topography in sacrificial gate layer prior to gate patterning | Electricity | 8 | Active |
| US9711598B2 | Two-dimensional condensation for uniaxially strained semiconductor fins | Electricity | 3 | Active |
| US9159835B2 | Two-dimensional condensation for uniaxially strained semiconductor fins | Electricity | 3 | Active |
| US9640537B2 | Non-silicon device heterolayers on patterned silicon substrate for CMOS by combination of selective and conformal epitaxy | Electricity | 2 | Active |
| US10249490B2 | Non-silicon device heterolayers on patterned silicon substrate for CMOS by combination of selective and conformal epitaxy | Electricity | 2 | Active |
| US11164974B2 | Channel layer formed in an art trench | Electricity | 1 | Active |
| US8878363B2 | Fermi-level unpinning structures for semiconductive devices, processes of forming same, and systems containing same | Electricity | 1 | Active |
| US10756198B2 | Fermi-level unpinning structures for semiconductive devices, processes of forming same, and systems containing same | Electricity | 0 | Active |
| US10304929B2 | Two-dimensional condensation for uniaxially strained semiconductor fins | Electricity | 0 | Active |
| US9865684B2 | Nanoscale structure with epitaxial film having a recessed bottom portion | Electricity | 0 | Active |
| US11631737B2 | Ingaas epi structure and wet etch process for enabling III-v GAA in art trench | Electricity | 0 | Active |
| US9680013B2 | Non-planar device having uniaxially strained semiconductor body and method of making same | Electricity | 0 | Active |
| US9768269B2 | Fermi-level unpinning structures for semiconductive devices, processes of forming same, and systems containing same | Electricity | 0 | Active |
| US9419140B2 | Two-dimensional condensation for uniaxially strained semiconductor fins | Electricity | 0 | Active |
Source: USPTO / EPO open patent data. Inventor disambiguation is heuristic; counts are objective bibliographic measures.