Semiconductor packages and methods of fabrication thereof
US9773719B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Nov 26, 2012 |
| Grant date | Sep 26, 2017 |
| Priority date | — |
| Expiry date | Oct 5, 2034 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/206
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
In accordance with an embodiment of the present invention, a semiconductor device includes a semiconductor chip having a first side and an opposite second side, and a chip contact pad disposed on the first side of the semiconductor chip. A dielectric liner is disposed over the semiconductor chip. The dielectric liner includes a plurality of openings over the chip contact pad. A interconnect contacts the semiconductor chip through the plurality of openings at the chip contact pad.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.