Non-volatile memory structure and manufacturing method thereof
US9773800B1 · kind B1 · utility
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18Claims
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Key dates
| Filing date | Aug 30, 2016 |
| Grant date | Sep 26, 2017 |
| Priority date | — |
| Expiry date | Aug 30, 2036 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D30/694
Abstract
The present invention provides a non-volatile memory structure, which includes a substrate, a gate dielectric layer disposed on the substrate, two charge trapping layers, disposed on two sides of the gate dielectric layer respectively and disposed on the substrate, a gate conductive layer disposed on the gate dielectric layer and on the charge trapping layers, wherein a sidewall of the gate conductive layer is aligned with a sidewall of one of the two charge trapping layers, and at least one vertical oxide layer, disposed beside the sidewall of the gate conductive layer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.