Vertical field effect transistor with wrap around metallic bottom contact to improve contact resistance

US9773913B1 · kind B1 · utility

Assignee

• International Business Machines Corporation · US

Inventors

• Karthik Balakrishnan · Houston, US
• Kangguo Cheng · Schenectady, US
• Pouya Hashemi · White Plains, US
• Alexander Reznicek · Troy, US

Key dates

• Filing date: May 6, 2016
• Grant date: Sep 26, 2017
• Expiry date: May 6, 2036

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10D64/62
• WIPO field: Semiconductors
• WIPO sector: Electrical engineering

Abstract

Semiconductor devices having vertical field effect transistor (FET) devices with reduced contact resistance are provided, as well as methods for fabricating vertical FET devices with reduced contact resistance. For example, a semiconductor device includes a vertical FET device formed on a substrate. The vertical FET comprises a lower source/drain region disposed on the substrate. The lower source/drain region comprises an upper surface, sidewall surfaces, and a bottom surface, wherein the bottom surface of the lower source/drain region contacts the substrate. A lower metallic contact is disposed adjacent to, and in contact with, at least one sidewall surface of the lower source/drain region, wherein the lower metallic contact comprises a laterally extended portion which laterally extends from the at least one sidewall surface of the lower source/drain region. A vertical source/drain contact is disposed adjacent to the vertical FET device and contacts the laterally extended portion of the lower metallic contact.