Integrated circuit chip assembled on an interposer
US9780015B2 · kind B2 · utility
0Cited by
3References
21Claims
0Family size
Assignees
Inventors
Key dates
| Filing date | Jul 7, 2016 |
| Grant date | Oct 3, 2017 |
| Priority date | — |
| Expiry date | Jul 7, 2036 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/18161
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A device includes a chip assembled on an interposer. An electrically-insulating layer coats an upper surface of the interposer around the chip. First metal lines run on the upper surface of the interposer and are arranged between conductive elements of connection to the chip. An end of each first metal line is arranged to extend beyond a projection of the chip on the interposer. A thermally-conductive via connects the end of the first metal line to a heat sink supported at an upper surface of the device.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.