3D semiconductor package interposer with die cavity
US9780072B2 · kind B2 · utility
20Cited by
82References
20Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | May 13, 2016 |
| Grant date | Oct 3, 2017 |
| Priority date | — |
| Expiry date | May 13, 2036 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/20755
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Disclosed herein is a method of forming a device, comprising mounting a plurality of first interconnects on one or more first integrated circuit dies. One or more second integrated circuit dies are mounted on a first side of an interposer. The interposer is mounted at a second side to the first integrated circuit dies, the plurality of first interconnects disposed outside of the interposer. The interposer is mounted to a first side of a substrate by attaching the first interconnects to the substrate, the substrate in signal communication with one or more of the first integrated circuit dies through the first interconnects.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.