Translation entry invalidation in a multithreaded data processing system
US9785557B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Oct 25, 2016 |
| Grant date | Oct 10, 2017 |
| Priority date | — |
| Expiry date | Oct 25, 2036 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2212/683
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
In a multithreaded data processing system including a plurality of processor cores, storage-modifying requests, including a translation invalidation request of an initiating hardware thread, are received in a shared queue. The translation invalidation request is broadcast so that it is received and processed by the plurality of processor cores. In response to confirmation of the broadcast, the address translated by the translation entry is stored in a queue. Once the address is stored, the initiating processor core resumes dispatch of instructions within the initiating hardware thread. In response to a request from one of the plurality of processor cores, an effective address translated by a translation entry being invalidated is accessed in the queue. A synchronization request for the address is broadcast to ensure completion of processing of any translation invalidation request for the address.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.