Devices, systems, and methods of reducing chip select
US9785603B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jul 18, 2016 |
| Grant date | Oct 10, 2017 |
| Priority date | — |
| Expiry date | Jul 18, 2036 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F13/385
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Several systems and methods of chip select are described. In one such method, a device maintains two identifiers, (ID_a and ID_m). When the device receives a command, it examines the values of ID_a and ID_m relative to a third reference identifier (ID_s). If either ID_a or ID_m is equivalent to ID_s, the device executes the command, otherwise, the device ignores the command. By using two different identification methods, a system has options in choosing to activate devices, being able to selectively switch between selecting multiple devices and single devices in a quick manner. In another such method, a device may have a persistent area that stores identification information such as an ID_a. Thus, system functionality may remain independent from any defect/marginality associated with the physical or logical components required for initial ID_a assignment of all devices in the system.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.