Patent · US Active

Method of manufacturing an integrated circuit substrate

US9786568B2 · kind B2 · utility

0Cited by

0References

25Claims

0Family size

Assignee

Infineon Technologies AG · DE

Inventors

Claudia Sgiarovello · Villach, AT
Martin Mischitz · Wernberg, AT
Andrew Christopher Graeme Wood · St. Jakob im Rosental, AT

Key dates

Filing date	Feb 19, 2016
Grant date	Oct 10, 2017
Priority date	—
Expiry date	Feb 19, 2036

Classification

Technology area (CPC H)Electricity
CPC primaryH01L23/5252
WIPO fieldSemiconductors
WIPO sectorElectrical engineering

Abstract

A method of manufacturing a wafer. The method includes providing a wafer that includes a plurality of semiconductor device structures, and testing at least one of the plurality of semiconductor device structures. Based on a test result, a substance is provided on a selected portion of the wafer to selectively configure a circuit element within the at least one of the plurality of semiconductor device structures.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.