Dual deep trenches for high voltage isolation
US9786665B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Aug 16, 2016 |
| Grant date | Oct 10, 2017 |
| Priority date | — |
| Expiry date | Aug 16, 2036 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D84/038
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A semiconductor device adopts an isolation scheme to protect low voltage transistors from high voltage operations. The semiconductor device includes a substrate, a buried layer, a transistor well region, a first trench, and a second trench. The substrate has a top surface and a bottom surface. The buried layer is positioned within the substrate, and the transistor well region is positioned above the buried layer. The first trench extends from the top surface to penetrate the buried layer, and the first trench has a first trench depth. The second trench extending from the top surface to penetrate the buried layer. The second trench is interposed between the first trench and the transistor well region. The second trench has a second trench depth that is less than the first trench depth.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.