EUV resist etch durability improvement and pattern collapse mitigation
US9791779B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Oct 14, 2015 |
| Grant date | Oct 17, 2017 |
| Priority date | — |
| Expiry date | Oct 14, 2035 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L21/0337
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method for patterning a substrate is described. The patterning method includes receiving a first patterned layer overlying a material layer to be etched on a substrate, wherein the first patterned layer is composed of a resist material having (i) material properties that provide lithographic resolution of less than about 40 nanometers when exposed to extreme ultraviolet radiation lithography, and (ii) material properties that provide a nominal etch resistance to an etch process condition. The first patterned layer is over-coated with an image reversal material such that the image reversal material fills and covers the first patterned layer. The patterning method further includes removing an upper portion of the image reversal material such that top surfaces of the first patterned layer are exposed, and removing the first patterned layer such that the image reversal material remains resulting in a second patterned layer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.