Patent · US Active

Method for producing interconnections for 3D integrated circuit

US9793162B2 · kind B2 · utility

2Cited by

2References

19Claims

0Family size

Assignee

COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES · FR

Inventors

Claire Fenouillet-Beranger · Grenoble, FR
Philippe Coronel · Barraux, FR

Key dates

Filing date	Oct 20, 2015
Grant date	Oct 17, 2017
Priority date	—
Expiry date	Dec 23, 2035

Classification

Technology area (CPC H)Electricity
CPC primaryH10D84/0149
WIPO fieldSemiconductors
WIPO sectorElectrical engineering

Abstract

Method for producing one or more connection elements for integrated circuit including the formation of sacrificial elements passing through a porous layer formed between two superimposed levels of transistors, then the removal of the sacrificial elements through the porous layer and their replacement by a conductor material before or after having produced a higher level transistor.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.