Non-volatile split gate memory cells with integrated high K metal gate logic device and metal-free erase gate, and method of making same

US9793281B2 · kind B2 · utility

Assignee

• Silicon Storage Technology, Inc. · US

Inventors

• Chien-Sheng Su · Saratoga, US
• Jeng-Wei Yang · Zhubei City, TW
• Feng Zhou · Ann Arbor, US

Key dates

• Filing date: Jun 13, 2016
• Grant date: Oct 17, 2017
• Expiry date: Jun 13, 2036

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10D30/6892

Abstract

A method of forming split gate non-volatile memory cells on the same chip as logic and high voltage devices having HKMG logic gates. The method includes forming the source and drain regions, floating gates, control gates, and the poly layer for the erase gates and word line gates in the memory area of the chip. A protective insulation layer is formed over the memory area, and an HKMG layer and poly layer are formed on the chip, removed from the memory area, and patterned in the logic areas of the chip to form the logic gates having varying amounts of underlying insulation.