Integrated circuits including LDMOS transistor structures and methods for fabricating LDMOS transistor structures
US9793394B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 14, 2016 |
| Grant date | Oct 17, 2017 |
| Priority date | — |
| Expiry date | Jun 14, 2036 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D62/822
Abstract
Integrated circuits including LDMOS transistor structures and methods for fabricating LDMOS transistor structures are provided. An exemplary method for fabricating an LDMOS transistor structure includes providing a semiconductor-on-insulator (SOI) substrate including a semiconductor layer overlying an insulator layer overlying a bulk layer. The method includes forming a gate structure overlying the substrate. A channel region is formed in the semiconductor layer under the gate structure. The method includes forming a source region overlying the substrate. Further, the method includes forming a drain region overlying the substrate. A drift region is located between the drain region and the gate structure. Also, the method includes forming contacts to the gate structure, the source region, and the drain region.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.