Semiconductor device having insulating pattern and method of forming the same
US9793399B2 · kind B2 · utility
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20Claims
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Key dates
| Filing date | Dec 17, 2014 |
| Grant date | Oct 17, 2017 |
| Priority date | — |
| Expiry date | Dec 17, 2034 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D64/691
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A semiconductor device includes a stressor and an insulating pattern. A device isolation layer is formed to define an active area on a substrate. A first gate electrode is formed on the active area. A second gate electrode is formed on the device isolation layer. A trench is formed in the active area between the first gate electrode and the second gate electrode. A stressor is formed in the trench. A cavity formed between the stressor and the device isolation layer and adjacent to the second gate electrode is disposed. An insulating pattern is formed in the cavity.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.