Command protocol for adjustment of write timing delay

US9798353B2 · kind B2 · utility

Assignees

• Advanced Micro Devices, Inc. · US
• ATI Technologies ULC · CA

Inventors

• Aaron Nygren · Birkenfeld, DE
• Ming-Ju Edward Lee · San Jose, US
• Shadi M. Barakat · Sunnyvale, US
• Xiaoling Xu · Santa Clara, US
• Toan Duc Pham · Cedar Park, US
• W. Fritz Kruger · Sunnyvale, US
• Michael John Litt · Toronto, CA

Key dates

• Filing date: Jun 18, 2013
• Grant date: Oct 24, 2017
• Expiry date: Oct 10, 2034

Classification

• Technology area (CPC G): Physics
• CPC primary: G06F13/1689
• WIPO field: Computer technology
• WIPO sector: Electrical engineering

Abstract

Apparatuses are provided for adjusting the write timing. For instance, the apparatus can include an address/control bus, a write clock data recovery (WCDR) signal bus, and a timing adjustment module. The address/control bus can be configured to concurrently enable a WCDR mode of operation and an active mode of operation. The WCDR signal bus can be configured to transmit WCDR data to a memory device during the WCDR mode of operation. And the timing adjustment module can be configured to adjust a timing based on a phase shift in the WCDR data.