Static random access memory (SRAM) with recovery circuit for a write operation
US9799394B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Apr 27, 2015 |
| Grant date | Oct 24, 2017 |
| Priority date | — |
| Expiry date | Apr 27, 2035 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C11/419
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A static random access memory (SRAM) including at least a memory cell array, a first data line, a second data line, a third data line and a driver circuit. The first data line is electrically coupled with the memory cell array. The second data line is electrically coupled with the memory cell array. The driver circuit is electrically coupled with the first data line, the second data line and the third data line. The driver circuit includes a recovery circuit electrically coupled with the first data line, the second data line and the third data line. During a write operation of the SRAM, the recovery circuit is configured to pull a voltage level of the first data line to a first voltage level when the recovery circuit is enabled.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.