Methods employing sacrificial barrier layer for protection of vias during trench formation
US9799559B1 · kind B1 · utility
Assignees
Inventors
Key dates
| Filing date | May 19, 2016 |
| Grant date | Oct 24, 2017 |
| Priority date | — |
| Expiry date | May 19, 2036 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L23/53266
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method includes, for example, providing an intermediate semiconductor structure comprising a metallic layer, a patternable layer disposed over the metallic layer, and a hard mask disposed over the patternable layer, the intermediate semiconductor structure comprising a plurality of vias extending through the hard mask onto the metallic layer, depositing a sacrificial barrier layer over the intermediate semiconductor structure and in the plurality of vias, removing a portion of the sacrificial barrier layer between the plurality of vias while maintaining a portion of the sacrificial barrier layer in the plurality of vias, forming a trench in the patternable layer between the removed portion of the sacrificial barrier layer and the plurality of vias, and removing the remaining portions of the sacrificial barrier layer from the plurality of vias.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.