Stable and reliable FinFET SRAM with improved beta ratio
US9799660B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | May 11, 2016 |
| Grant date | Oct 24, 2017 |
| Priority date | — |
| Expiry date | May 11, 2036 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D89/10
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Fabrication method for a semiconductor memory device and structure are provided, which includes: providing at least two mask layers over a pair of fin structures extended above a substrate, wherein a first mask layer of the at least two mask layers is orthogonal to a second mask layer of the at least two mask layers; and patterning the pair of fin structures to define a pass-gate transistor, wherein the first mask layer facilitates removing of a portion of a first fin structure of the pair of fin structures to define a first pass-gate fin portion of the pass-gate transistor, and the second mask layer protects a second fin structure of the pair of fin structures to define a second pass-gate fin portion of the pass-gate transistor.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.