Methods of forming a gate structure on a vertical transistor device
US9799751B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Apr 19, 2016 |
| Grant date | Oct 24, 2017 |
| Priority date | — |
| Expiry date | May 21, 2036 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D84/0195
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
One illustrative method disclosed herein includes forming a multi-layered sidewall spacer (MLSS) around a vertically oriented channel semiconductor structure, wherein the MLSS comprises a non-sacrificial innermost first spacer (a high-k insulating material), a sacrificial outermost spacer and at least one non-sacrificial second spacer (a metal-containing material) positioned between the innermost spacer and the outermost spacer, removing at least a portion of the sacrificial outermost spacer from the MLSS while leaving the at least one non-sacrificial second spacer and the non-sacrificial innermost first spacer in position and forming a final conductive gate electrode in place of the removed sacrificial outermost spacer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.