Computational resource pipelining in general purpose graphics processing unit
US9804995B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jan 14, 2011 |
| Grant date | Oct 31, 2017 |
| Priority date | — |
| Expiry date | Nov 24, 2033 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F15/17325
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
This disclosure describes techniques for extending the architecture of a general purpose graphics processing unit (GPGPU) with parallel processing units to allow efficient processing of pipeline-based applications. The techniques include configuring local memory buffers connected to parallel processing units operating as stages of a processing pipeline to hold data for transfer between the parallel processing units. The local memory buffers allow on-chip, low-power, direct data transfer between the parallel processing units. The local memory buffers may include hardware-based data flow control mechanisms to enable transfer of data between the parallel processing units. In this way, data may be passed directly from one parallel processing unit to the next parallel processing unit in the processing pipeline via the local memory buffers, in effect transforming the parallel processing units into a series of pipeline stages.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.