Computation memory operations in a logic layer of a stacked memory
US9804996B2 · kind B2 · utility
4Cited by
2References
29Claims
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Key dates
| Filing date | Dec 21, 2012 |
| Grant date | Oct 31, 2017 |
| Priority date | — |
| Expiry date | Dec 28, 2034 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY02D10/00
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Some die-stacked memories will contain a logic layer in addition to one or more layers of DRAM (or other memory technology). This logic layer may be a discrete logic die or logic on a silicon interposer associated with a stack of memory dies. Additional circuitry/functionality is placed on the logic layer to implement functionality to perform various computation operations. This functionality would be desired where performing the operations locally near the memory devices would allow increased performance and/or power efficiency by avoiding transmission of data across the interface to the host processor.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.