Enhanced erasing of two-terminal memory
US9805794B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | May 19, 2015 |
| Grant date | Oct 31, 2017 |
| Priority date | — |
| Expiry date | May 19, 2035 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2013/0092
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Two-terminal memory can be set to a first state (e.g., conductive state) in response to a program pulse, or set a second state (e.g., resistive state) in response to an erase pulse. These pulses generally provide a voltage difference between the two terminals of the memory cell. Certain electrical characteristics associated with the pulses can be manipulated in order to enhance the efficacy of the pulse. For example, the pulse can be enhanced or improved to reduce power-consumption associated with the pulse, reduce a number of pulses used to successfully set the state of the memory cell, reduce wear or damage to the memory cell, or to improve Ion or Ioff distribution associated with changing the state of the memory cell.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.